1. Field of the Invention
The present invention relates to a method of forming an etching mask in a process of fabricating a semiconductor device, an etching method using the etching mask, and a method of fabricating a semiconductor device including the etching method.
2. Description of the Related Art
Recently, as components of semiconductor devices have been manufactured to have smaller sizes due to requests for large-scale integration (LSI), wires having a line width of, for example, 45 nm or 32 nm have been required. However, an etching mask for realizing this line width cannot be obtained using a conventional photolithography technology. Although an extreme ultra-violet (EUV) exposure technology using EUV light having a wavelength of 13.5 nm has been developed recently, such EUV exposure technology has not been commercialized so far.
Under the circumstances, a double-patterning technology has been highlighted as a potential measure to address this problem. For example, in the double-patterning technology disclosed in Japanese Patent Laid-open Publication No. 2007-022742 (FIGS. 1 and 3, hereinafter, referred to as reference 1), the following operations are performed. First, a lower sacrificial layer and an upper sacrificial layer are sequentially formed on a layer that is to be etched. Next, a first resist layer is applied on the upper sacrificial layer, and then, the first resist layer is patterned using a first photo mask to form a first resist mask having a first pattern. Thereafter, the first pattern is transferred onto the upper sacrificial layer by using the first resist mask.
Then, the first resist mask is removed and a cleaning process is performed, and a second resist layer is applied on the lower sacrificial layer so as to cover the upper sacrificial layer, onto which the first pattern has been transferred by etching. After that, the second resist layer is patterned using a second photo mask to form a second resist mask having a second pattern. Next, the first and second patterns are transferred onto the lower sacrificial layer using the upper sacrificial layer which has the first pattern transferred thereon and remains on the lower sacrificial layer, and using the second resist mask.
Finally, the layer to be etched is etched using the lower sacrificial layer on which the first and second patterns have been transferred.
As described above, according to the above-described double-patterning technology, patterning using the resist mask is performed twice and also transferring (etching) is performed twice. By doing this, patterns having an interval half of the interval of a pattern formed by single patterning and a single etching operation may be formed.
However, in the above-described double-patterning technology, etching is performed using a photomask, and this etching is performed again. Therefore, a wafer needs to be inserted/drawn into/from an etching device twice, and thus, the method flow becomes complex. Moreover, when a trimming operation of the resist mask or a side wall transfer operation is employed in order to realize finer patterns, the method flow becomes even more complex.
The complex method flow (or the complex wafer conveying path) reduces the yield of a method of manufacturing semiconductor devices, and accordingly, an etching method with a simple flow is necessary.